It’s quite surprising AMD opted to release these details so early – but for those interested in technology, we’re not complaining.Let’s start things with the stuff we already know, but is reconfirmed – DDR4 support (though supported memory speeds weren’t mentioned), SP3 socket (the same as the older generations), 7nm+ (there was a typo in this roadmap, but it was confirmed in the video presentation that it is 7nm+), PCIe 3 and 4 support (though the number of lanes wasn’t specified).For new information though – it retains the same TDP as the second generation – between 120 and 225W. So till now, Zen and Zen 2 had two core complexes on the same die with each CCX consisting of 4 cores. With "Zen 2," AMD reduced the CPU chiplet to only containing CPU cores, L3 cache, and an Infinity Fabric interface, talking to an I/O controller die elsewhere on the processor package. At the time, the 8-core "Zeppelin" die featured two CCX with four cores, each. AMD confirmed that we’ll see a different socket (SP5), and currently they’re still adding features to the chips (meaning it’s not finalized). It is a chip that has been completely revamped from the group up and focuses on When asked about what kind of performance gain Milan's CPU core microarchitecture, which is known as Zen 3, will deliver relative to the Zen 2 microarchitecture that Rome relies on in terms of instructions processed per CPU clock cycle (IPC), Norrod observed that -- unlike Zen 2, which was more of an evolution of the Zen microarchitecture that powers first-gen Epyc CPUs -- Zen 3 will be based on a completely new architecture.Norrod did qualify his remarks by pointing out that Zen 2 delivered a bigger IPC gain than what's normal for an evolutionary upgrade -- AMD has said it's about 15% on average -- since it implemented some ideas that AMD originally had for Zen but had to leave on the cutting board. We also see the same number of cores too, 64 Cores / 2x. In this documentation it specifically mentions a custom design – so (and this is pure speculation), some customers get SMT-4 and higher die count chips… though once again, this is pure speculation and an attempt to make the old rumors fit.Let’s also bring Genoa / Zen 4 into the equation, although we know much less about this than we do Zen 3 and Milan. The second-generation Zen did numerous things to the architecture which we’ve discussed a lot in the past, but one big change was the Level 3 cache, which was doubled in size.But, essentially each ‘chiplet’ was comprised of 8 CPU cores, and those 8 cores were then further split into two ‘CCXs’, each housing its own 4 cores and 16MB level 3 cache (so 4 cores and 16MB x 2 CCXs = 8 cores and 32MB total). It was Charlie over at SemiAccurate who’d originally said that there are more dies on Milan (he believed up to 15), but this is probably not true… unless they’re something not CPU related, such as GPU cores or HBM2 (this isn’t a piece of info I heard, to be clear… I’m just providing a way to balance his usually good info with this official confirmation).Another huge thing we can see is a shot of the CCX and CPU layout compared to that of Rome, and the differences in the Level 3 cache between a Zen 2 CCX and Zen 3 CCX are palpable.
But, when AMD first launched both the original Ryzen CPUs and the first-gen of Epyc, Lisa Su promised that there would be forwards/backwards compatibility until 2020.So, we’ve known that if you have bought say an X370 motherboard back in 2017 along with a Ryzen 7 1700X, you should be able to switch that CPU out with say Ryzen 7 4700X in 2020, as long as you do a BIOS update.
"Other rumors have pointed out to a 50% increase in overall floating-point performance.
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